For system level packaging of a power MOSFET device, sometimes a bottom source power MOSFET is needed to optimize chip arrangement and/or to reduce packaging-related parasitic interconnecting impedance. Such an example can be found in U.S. application Ser. No. 11/830,951 that, inter alia, described a multi-die semiconductor package for DC-DC boost converter application having a lead-frame with a grounded die pad; a vertical bottom source N-channel MOSFET placed atop the die pad; and an anode-substrate Schottky diode with its anode connected to the drain of the vertical MOSFET. The Schottky diode die and the vertical MOSFET die are co-packaged atop the single die pad in a stacked way with the Schottky diode die atop the vertical MOSFET die for minimized vertical MOSFET source inductance and easy heat sinking. However, as the source and gate are usually formed on the top of the die in the art, it is difficult to simply mount the MOSFET die upside down due to difficulties in making contact to the gate pad.
As it offers advantages of bulk device electrical resistance reduction, bulk device thermal resistance reduction while maintaining low profile, the ability of making thin chips with a reduced substrate thickness of power semiconductor devices has also become very desirable in the semiconductor industry.
FIG. 7A is a cross sectional view of a bottom-source lateral diffusion MOS (BS-LDMOS) device described in U.S. Pat. No. 7,554,154, entitled “Bottom source LDMOSFET structure and method” by Hebert et al. and granted on Jun. 30, 2009. An implanted deep sinker region 115 is used to achieve the bottom-source device configuration. The BSLDMOS device is supported on a P+ substrate 105 functioning as a bottom source electrode. A layer of P− epitaxial layer 110 is supported on top of the substrate 105. A deep sinker region 115 doped with P+ dopant ions below an active cell area in the device is formed in the epitaxial layer at a depth and extended laterally to a bottom of a drain drift region 125 to compensate some of the N− dopant in the accumulation of the transistor for tailoring a dopant profile of N-drift region 125 to minimize the gate-drain capacitance while maintaining a low drain to source resistance R.sub.dson. The deep sinker region 115 further extends vertically both downward to the bottom P+ substrate 105, and upward to a body region 150 that forms a channel at a top surface under a gate oxide 135. The sinker regions 115 functions as a combined channel and also as a buried source body contact for contacting to a P+ body contact region 155 that is formed near the top surface formed as a top trench covered by a source metal 170-S surrounded by N+ doped source region 160. A terrace-shaped gate 140 surrounded by a gate spacer 165 and covered by a gate shield metal 170-G is disposed above the gate oxide layer 135 formed on the top surface between the source region 160 and the drain drift region 125. The gate 140 thus controls the current flow between the source region 160 and the drain drift region 125 through the channel form by body region 150 under the gate 140 to function as a lateral MOS device. The drain region 125 is disposed below a field oxide 130 covered by a BPSG layer 180 and optionally a passivation layer 185. A drain contact opening is etched through the passivation layer 185 and the BPSG layer 180 for the top drain metal 199 to contact the drain region 125 via a contact N+ dopant region 190 with reduce contact resistance. The terrace-shaped oxide 130 and 135 below the terrace gate 140 as shown may be formed by different methods. The methods include the processes of growing or depositing the oxide and etching from the channel region or by using a LOCOS type of oxide deposition process. The terrace-shaped gate 140 has a longer gate length and field plating over the drain extension without increasing the cell pitch. The terrace gate 140 provides necessary link for current to flow between the channel and the drain under the gate oxide 135 and field oxide 130 with reduced gate-drain capacitance. However, the corresponding cell pitch is a concern with such structure and approach. That is, the achievable cell pitch can be too large as the sinker region 115 takes up too much room.
With the advent of through substrate via (TSV) technology in the prior art such as illustrated in FIG. 7B, a bottom source power MOSFET device can now be made by flipping the chip over so its device-side is facing down and having its device-side gate metal (bottom) re-routed, with an isolated conductive via, to its substrate-side gate metal (top). Otherwise, there is basically no change to other parts of the device structure nor to its front end fabrication process. As an example, the structure of the isolated conductive via can be an oxide-lined metal fill. Notwithstanding these advantages, the isolation of TSV and associated fabrication steps on the backside of a thinned wafer still undesirably bring up process complexity and cost. Therefore, device structure and process steps simpler than these prior arts are still desired.